Links to Selected Research Papers:
Multi–Gate MOSFETs:
- Performance assessment of nanoscale double and triple gate FinFETs, Semiconductor Science and Technology, vol. 21, no. 4, pp. 409-421, 2006.
- Improving fMAX/fT ratio in FinFETs using source/drain extension region engineering, Electronics Letters, vol. 44, no. 13, pp. 825-827, 2008.
- Comparative analysis of nanoscale MOS device architectures for RF applications, Semiconductor Science and Technology, vol. 22, no. 5, pp. 481-491, 2007.
- Optimizing FinFET geometry and parasitics for RF applications, In Proc. IEEE SOI Conference, pp. 123-124, 2008.
- Device design considerations for nanoscale double and triple gate FinFETs, In Proc. IEEE SOI Conference, pp. 96-98, 2005.
Low Power Operation of Multi–Gate MOSFETs:
- Design and optimization of FinFETs for ultra–low–voltage analog applications, IEEE Transactions on Electron Devices, vol. 54, no.12, pp. 3308-3316, 2007.
- Source/Drain extension region engineering in FinFETs for low-voltage analog applications, IEEE Electron Device Letters, vol. 28, no. 2, pp. 139–141, 2007.
- Insights into gate–underlap design in FinFETs for ultra–low voltage analog performance, In Proc. IEEE SOI Conference, pp. 33-34, 2007.
- Source/Drain extension region engineering in nanoscale double gate SOI MOSFETs for low voltage analog applications, In Proc. IEEE SOI Conference, pp. 141-142, 2006.
Junctionless Transistors:
- Impact of channel doping and spacer architecture on analog/RF performance of low power junctionless MOSFETs, Semiconductor Science and technology, vol. 30, article 015002, 2015.
- Back bias induced dynamic and steep subthreshold swing in junctionless transistors, Applied Physics Letters, vol. 105, article 033503, 2014.
- Revisiting the doping requirement for low power junctionless MOSFETs, Semiconductor Science and technology, vol. 29, article 075006, 2014.
- Occurrence of zero gate oxide thickness coefficient in junctionless transistors, Applied Physics Letters, vol. 102, article 203509, 2013.
- Single transistor latch phenomenon in junctionless transistors, Journal of Applied Physics, vol. 113, article 184503, 2013.
- Ultra low power junctionless MOSFETs for subthreshold logic applications, IEEE Trans. Electron Devices, vol. 60, no. 5, pp. 1540-1546, 2013.
- Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory, Applied Physics Letters, vol. 101, no. 26, article 263503, 2012.
- High performance junctionless MOSFETs for ultra low power analog/RF applications, IEEE Electron Device Letters, vol. 33, no. 10, pp. 1477-1479, 2012.
- Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates, IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2308- 2313, 2012.
- Bipolar effects in unipolar junctionless transistors, Applied Physics Letters, vol. 101, article 093507, 2012.
- Junctionless nanowire transistor (JNT): properties and design guidelines, Solid-State Electronics, vol. 65-66, no. 1, pp. 33-37, 2011.
- Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions, Science of Advanced Materials, vol. 3, no. 3, pp. 1-6, 2011.
- Mobility improvement in nanowire Junctionless transistors by uniaxial strain, Applied Physics Letters, vol. 97, article no. 042114, 2010.
- Junctionless nanowire transistor (JNT): properties and design guidelines, In Proc. European Solid State Device Research Conference (ESSDERC), pp. 357-360, 2010.
- Characterization of junctionless Z-RAM cell, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper E-1-2, 2010.
- Nanowire zero-capacitor DRAM transistors with and without junctions, IEEE Conference on Nanotechnology (IEEE-NANO), pp. 242-245, DOI: 10.1109/NANO.2010.5697888, 2010.
Transistors for Biosensing Applications:
- Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications, Nanotechnology, vol. 26, article 145201, 2015.
Circuit Design:
- Non–classical channel design in MOSFETs for improving OTA gain–bandwidth trade–off, IEEE Transactions on Circuits and Systems-I, vol. 57, no. 12, pp. 3048-3054, 2010.
- Junctionless 6T SRAM cell, IET Electronics Letters, vol. 46, no. 22, pp. 1491-1493, 2010.
- 6-T SRAM cell design with nanoscale double gate SOI MOSFETs: impact of source/drain engineering and circuit topology, Semiconductor Science and Technology, vol. 23, no. 7, article 075049, 2008.
- High temperature performance of OTA with non–ideal double gate SOI MOSFETs, In Proc. IEEE SOI Conference, pp. 153-154, 2009.
- Optimizing spacer–to–straggle ratio in gate underlap SOI MOSFETs for low voltage analog and digital circuits, 215th Electrochemical Society Meeting, In Proc. ECS Transactions (SOI Device Technology), vol. 19, no. 4, pp. 283-288, 2009.
- Insights into gate–underlap design in double gate based 6T SRAM cell for low voltage applications, In Proc. IEEE SOI Conference, pp. 61-62, 2008.
Single/Double Gate SOI MOSFETs:
- Optimally designed moderately inverted double gate SOI MOSFETs for low-power RFICs, Semiconductor Science and Technology, vol. 27, article 125004, 2012.
- How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra–low–voltage analog/RF applications?, Solid-State Electronics, vol. 52, no. 12, pp. 1895-1903, 2008.
- High tolerance to gate misalignment in low voltage gate–underlap double gate MOSFETs, A. Kranti and G.A. Armstrong, IEEE Electron Device Letters, vol. 29, no. 5, pp. 503-505, 2008.
- Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications, Semiconductor Science and Technology, vol. 23, no. 4, article 045001, 2008.
- Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low voltage applications, Microelectronic Engineering, vol. 84, no.12, pp. 2775-2784, 2007.
- Optimization of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFET with high–K gate dielectrics, Semiconductor Science and Technology, vol. 21, no. 12, pp. 1563-1572, 2006.
- Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: analytical model and design considerations, Solid-State Electronics, vol. 50, no. 3, pp. 437-447, 2006.
- Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs, Semiconductor Science and Technology, vol. 20, no. 5, pp. 423-429, 2005.
- Analysis of static and dynamic performance of short channel double gate SOI MOSFETs for improved cut-off frequency, Japanese Journal of Applied Physics, vol. 44, no. 4B, pp. 2340-2346, 2005.
- Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications, Solid-State Electronics, vol. 48, no.6, pp. 947-959, 2004.
Surrounding Gate MOSFETs:
- Design and optimization of thin film fully depleted vertical surrounding gate (VSG) MOSFETs for enhanced short channel immunity, Solid-State Electronics, vol. 46, no.9, pp. 1333-1338, 2002.
- Optimization for improved short channel performance of surrounding/cylindrical gate (SGT) MOSFETs, Electronics Letters, vol. 37, no. 8, pp. 533-534, 2001.
- An analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET, Microelectronic Engineering, vol. 56, no. 3-4, pp. 241-259, 2001.
- Temperature dependent threshold voltage analysis of surrounding/cylindrical gate fully depleted thin film SOI MOSFET in the range 77 to 520K, Microelectronic Engineering, vol. 49, no. 3-4, pp. 273-286, 1999.
AlGaN/GaN HEMTs:
- Comprehensive analysis of small signal parameters of fully strained and partially relaxed high Al-content lattice mismatched AlmGa1-mN/GaN HEMTs, IEEE Trans. Microwave Theory and Techniques, vol. 51, no. 2, pp. 607-617, 2003.
- An accurate charge control model for spontaneous and piezoelectric polarization dependent two-dimensional electron gas (2-DEG) sheet charge density of lattice mismatched AlGaN/GaN HEMTs, Solid-State Electronics, vol. 46, no. 5, pp. 621-630, 2002.
- Impact of strain relaxation of AlmGa1-mN layer on 2-DEG sheet charge density and current voltage characteristics of lattice mismatched AlmGa1-mN/GaN HEMTs, Microelectronics Journal, vol. 33, no. 3, pp. 205-212, 2002.
Bipolar Transistors:
- Optimization of trench isolated bipolar transistors on SOI substrates by 3D electro–thermal simulations, Solid-State Electronics, vol. 51, no. 9, pp. 1212-1228, 2007.